1. Field of the Invention
The present invention relates to an electronic system and, more particularly, to a frequency synthesizer having a fractional-N control circuit that operates as a modulator to selectively apply any fractional ratio to a multi-modulus frequency divider within, for example, a feedback loop of a phase locked loop (PLL).
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art or conventional by virtue of their inclusion within this section.
Within nearly every electronic subsystem is some sort of generator that produces cyclical waveforms. The waveform generator is oftentimes referred to as an oscillator. Oscillators are generally rated depending on their stability and accuracy, frequency adjustability (i.e., tunability), and power consumption. A piezoelectric crystal resonator is commonly used to provide a reference frequency that is fixed and generally considered the resonant frequency of the piezoelectric crystal—sometimes referred to as the crystal reference frequency FX. This reference frequency can thereafter be tuned using, for example, a phase-locked loop (PLL). Usually FX is too high so it is first divided down Q times by a reference frequency divider and becomes the reference frequency FR for the phase frequency detector (PFD). Thus, FR=FX/Q. Then the PLL employs a divider within its feedback loop to selectively increase the PFD's reference frequency FR. Thus, the resonator output frequency can be tuned using what will henceforth be referred to as a “frequency synthesizer.”
There are numerous ways in which to design a frequency synthesizer using a PLL. For example, the divider within the feedback loop of the PLL can be modified in integer increments. Thus, output from the frequency synthesizer will be in integer-N multiples of the reference frequency FR. In a traditional PLL implementation, the output will be represented as the voltage-controlled oscillator output, and will transition at a frequency of FVCO. Thus, FVCO=N*FR=N/Q*FX. An unfortunate aspect of integer-N frequency dividers is that the selectable discrete frequencies of FVCO is dependent on the value of N. The frequency spacing, oftentimes referred to as the minimum frequency resolution, or minimum channel spacing, using an integer-N divider can, in some instances, be too high for an intended application. Another issue is that for some applications, the integer N must be very large, and results in high phase noise.
Given that frequency synthesizers are used in a wide variety of applications, including FM radios, radar systems, cellular and PCS telephone systems, test equipment such as spectrum analyzers and signal generators, it would be desirable to implement a frequency synthesizer having a smaller minimum channel spacing. In order to achieve a smaller minimum channel spacing, fractional-N dividers are needed. In addition to achieving smaller channel spacing, fractional-N dividers allow small divide values to achieve the same channel spacing, which reduces the phase noise.
A fractional-N divider within the feedback loop can produce a synthesizer output of FVCO=FR(N+n/d). Thus, in addition to the integer divide factor N, a fractional-N divider will introduce fractions between integers set by a numerator value (n) divided by a denominator value (d). For example, when d=8, n may be an integer from 0 to 7. This example will increase the integer PLL resolution by a factor of 8 by adding 7 divide values between N and N+1. Thus the channel spacing is ⅛ of an integer PLL.
A fractional-N divider usually comprises a fractional-N control logic circuit and an integer-N divider. The divide value of the integer-N divider is switched between two integer values in a manner set by the fractional-N control logic circuit. Thus the average divide value is a fraction number. The way a fractional-N divider works causes signal spurs that are not usually seem on an integer divider, because each time the divide value changes, the PLL makes an abrupt phase correction. To minimize the spurs, the sequence of divide value should be optimized. One approach is delta-sigma modulation. To meet an even higher performance requirement, a compensation circuit could be used to cancel the signal spurs.
One of the desired features of a frequency synthesizer with fractional-N divider is high resolution, or small frequency spacing. The known architecture of a fractional-N divider requires the denominator d to be 2m (where m is an integer), which means 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, . . . , etc. Many fractional divide values are missing because the steps of the denominator are large. It is desirable to be able to use arbitrary integers for the denominator to further increase the resolution. Furthermore, it is also desirable that the spurious noise generated by the fractional-N divider be as small as possible.